1. Field of the Invention
The present invention relates generally to electrostatic discharge protection for semiconductor integrated circuitry and more particularly to an improved layout structure/pattern for electrostatic discharge protection
2. Background of the Invention
Static electricity has been an industrial problem for centuries. Since ancient time, people employed basic grounding and flame ionization techniques to dissipate static electricity and to refrain from ignition to combustible objects. The age of electronics brought with it new problems associated with static electricity and electrostatic discharge (“ESD”). And as electronic devices become faster and smaller, their sensitivity to ESD also increases.
Static electricity is defined as an electrical charge caused by an imbalance of electrons on the surface of a material. ESD is defined as the transfer of charge between bodies at different electrical potentials. ESD can change the electrical characteristics of a semiconductor device by either degrading or destroying it. The ESD damage may be either a catastrophic failure or a latent defect which may cause the semiconductor device no longer function or be partially degraded and experience premature failure. It will increase the associated costs for repair, replacement, and et al.
The protection of integrated circuits from ESD has received a lot of attention.
Many researchers in this field have proposed solutions to protect submicron devices without requiring any increase of silicon chip area. Because die size is the major cost factor for silicon fabricated products, layout rules followed by many modern time ICs need to be adjusted. According to conventional layout rules, the distance between two adjacent regions, such as between a well of a conductivity type and a heavily doped region, takes a lot of circuit area especially within high voltage area of, for example, a TFT Driver IC. The outermost ESD circuit device within an input/output circuit (“I/O”) will induce ESD disaster if the ESD circuit device follows the same conventional layout rules. It may not be able to safeguard the whole chip against ESD because the breakdown voltage of internal circuit will be lower than the breakdown voltage of I/O circuit. On the other hand, if the ESD circuit device follows that same layout rules as internal circuit, it will affect the durability of the ESD circuit when the IC is not connected to the circuit board and/or power-off and/or floating.
Referring now to FIG. 1, an example of a prior art layout pattern of a heavily doped region in a well is shown. A p type heavily doped region 30 and an n type heavily doped region 40 are formed in a p-well 10 and an n-well 20, respectively. A distance between a p type heavily doped region edge 300 and an n type well edge 200 is S1. A distance between an n type heavily doped region edge 400 and the n type well edge 200 is S2. Generally, S1 and S2 will be maintained at the same distance.
However, in order to reduce silicon chip area, the layout rules of the internal circuit need to be adjusted. As a result, the ESD device within I/O circuit will not be able to function properly to protect the internal circuit from power noise damage. On the other hand, reducing the distance S1 and S2 to safeguard the internal circuit will affect the ESD current clamping ability when the IC is not connected to the circuit board and/or power-off and/or floating.